The present invention relates in general to a computer system and pertains more particularly to a system that is constructed quite inexpensively employing on the order of 80 integrated circuits and having the capability of communicating with a number of port devices.
One object of the present invention is to provide an improved computer system having manual reset means for controlling the central processing unit.
Another object of the present invention is to provide an improved addressing scheme for the random access memory of the system.
A further object of the present invention is to provide a computer system that has the capability of a video output that may be either alpha numeric or graphic.
Still another object of the present invention is to provide a computer system having a video output for providing different size characters. In accordance with the present invention the output can be controlled so as to display either 32 characters per line or 64 characters per line.
Another object of the present invention is to provide an improved computer system for providing a chain control of the video RAMs or alternatively control directly from the data bus of the CPU.
Another object of the present invention is to provide a computer system having the capability of graphic display. In accordance with the invention, the display field is demarcated into rectangular segments with each segment in turn sectioned into, for example, 6 parts which are individually selectable by data bus information.
Still another object of the present invention is to provide an improved computer system having a novel keyboard entry scheme.
A further object of the present invention is to provide an improved computer system having a novel port control particularly useful with a port device such as a tape recorder/player.
To accomplish the foregoing and other objects of this invention, there is provided a computer system including a central processing unit, means for storing instructions for the central processing unit disclosed as a read-only memory (ROM), random access memory means for storing data, keyboard means for entering data into the computer system, and display means disclosed in the form of a conventional CRT television display. Connections from the central processing unit, (CPU) include control lines, a plurality of data lines, forming a data bus and a plurality of address lines, forming an address bus. The data lines are bidirectional whereas the address lines are uni-directional. The CPU interrogates other components of the computer system by way of the address bus to indicate where the data it is looking for is located. The data bus is the means of communication for data both to and from the CPU. The ROM contains the instructions for the CPU indicating to the CPU what to do, how to carry out the instruction, and where to put the data after the instruction is completed. The CPU essentially looks to the ROM for instructions and then follows the instructions of the ROM. In all communications, the CPU applies address locations to both the ROM, RAM, and keyboard. However, address decoding determines which of these actual memories the CPU is looking for. In the system of this invention only the CPU communicates with all other sections. For example, data is to be transferred from the ROM into the RAM, the transfer is accomplished by way of the CPU. The keyboard means enables entry of instructions and data to the CPU. The system of this invention also includes a video random access memory (video RAM) which couples to a video processing section which in turn couples to a video output terminal or monitor such as a television receiver. Data in the video RAM is automatically displayed on the monitor.
In accordance with the present invention, there is provided a means for readily selecting different capacity memories especially with regard to the random access memory of the computer system. In this regard the system of the present invention employs an address decoder for ROM/RAM selection. The address decoder is responsive to an address code from the central processing unit for providing separate outputs, some of which at least correspond to different coded inputs representative of different capacity memories. At the output of the address decoder, there is a selection means for selecting different outputs from the address decoder to provide a memory enable signal. The address decoder in accordance with the present invention preferably decodes the higher order address lines, specifically four such lines, with the output of the decoder providing up to 8 output signals, only one of which at a time is active. The selection means preferably includes a selection shunt means having input terminals coupling to the address decoder and with some of its output terminals commonly tied to provide the memory enable signal. One section of the shunt preferably contains 4 shorting bars, commonly tied at their output terminals. For a 4K memory capacity, one bar is shorted, for 8K, two bars are shorted, for 12K, three bars are shorted, and for 16K, all four bars are shorted. In the disclosed embodiment this means that the enabling signal for the random access memory is active all the way from address 4.0..0..0. to address FFFF.